1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a dynamic random access memory (DRAM) device. More specifically, the present invention is concerned with improvements in speeding up the operation (cycle time) of the DRAM device.
Nowadays, the general DRAM devices employ a memory cell made up of one transistor and one capacitor and achieve high-speed operation. Comparatively, the DRAM device does not have a data read speed as high as that of a ROM (Read Only Memory) device because the data read operation is performed in a high-impedance state in which a capacitor stored in a memory cell is shared by a bit line. Further, data stored in the cell is destroyed after the data is read therefrom, and thus data must be amplified by sense amplifiers and then rewritten into the cells connected to the same word line as the above cell. The address access time is as low as 1/5-1/6 of the operation speed of a CPU. Hence, even when an I/O having a capability of transferring data at a high speed is employed, the latency is equal to 5-10.
In the data write operation, data stored in the cells connected to the same word line as a cell into which data should be written are destroyed. Hence, data are read from the cells connected to the same word line, and then a restore operation is carried out. Thus, the write cycle of the DRAM device is not short as that of an SRAM (Static Random Access Memory) device.
With the above in mind, the present invention is directed to providing a semiconductor memory device having a write cycle as short as that of the SRAM device and a read cycle as short as that of the ROM device and having a cell area less than that of the SRAM device.
In order to facilitate understanding the invention, a description will now be given of art related to the present invention.
2. Description of the Related Art
A DRAM device used in 1970s employs a memory cell formed by three transistors. FIG. 1 shows the structure of such a DRAM device. One memory cell consists of a driver transistor Q1, a read transistor Q2 and a write transistor Q3. A cell capacitor (illustrated by broken lines) provides a storage capacitance and is connected to the gate of the driver transistor Q1. The read transistor Q2 is connected by read word lines Read.sub.-- WLn (n=0, 1, . . . , n). The write transistors Q3 are controlled by write word lines Write.sub.-- WLn. The read transistors Q2 are connected to read bit lines Read.sub.-- BLn, and the write transistors Q3 are connected to write bit lines Write.sub.-- BLn. In the following description, the above symbols "Read.sub.-- " and "Write.sub.-- " are abbreviated as "R" and "W", respectively.
When data is read from a memory cell, the read transistor Q2 is turned ON by the read word line RWL. The cell capacitor is connected to the gate of the driver transistor Q1. Hence, even when the read transistor Q2 is ON, the potential of the memory capacitance (cell capacitor) retains, and data stored therein is not destroyed. Thus, there is no need to perform the data rewrite (restore) operation after the read operation, and the read cycle can be reduced. Further, data is read from the memory cell in a current drive formation in which the driver transistor Q1 is turned ON and the charge of the read bit line RBL is caused to flow to the ground GND when the charge is stored in the cell capacitor. Hence, the potential of the read bit line RBL is changed rapidly, and data can be read from the memory cell at a comparatively high speed.
In contrast, when data is written into a memory cell, data stored in the memory cells connected to the same word line as the memory cell are destroyed. This will be described with reference to FIG. 2. The potentials of the write bit lines WBL are applied to all the cells selected by the write word line WWL because the cell capacitors of these cells are connected to the write bit lines WBL. For example, when the write word line WWL0 is selected, the potentials of the write bit lines WBL0, WBL1, . . . , WBLn are applied to the cell capacitors of the memory cells A, B, . . . connected to the write word line WWL0. That is, data of the write bit lines WBL0, WBL1, WBLn are written into the cell capacitors of the memory cells A, B, . . . , via the respective write transistors Q3.
Hence, as shown in data write cycles of the cells A and B in FIG. 2, one write cycle requires a data read operation and a data restore (rewrite) operation. For example, when data should be written into the cell A, the read word line RWL0 is driven, and data stored in the cells connected to the read word line RWL0 are read to the read bit lines RBL0, RBL1, and so on. The read data are latched in sense amplifiers (not shown) connected to the bit lines, and the restore operation is performed so that the latched data are rewritten in the memory cell while the target cell A is supplied with write data via the write bit line WBL0 at the timing of the above restore operation.
In FIG. 2, when data is written into the cell A, data (high level) of the cell B is read to the read bit line RBL1, and the write bit line WBL1 is driven so as to become high by the restore operation. Hence, the high-level data is rewritten into the cell B.
As described above, the write operation requires two operations of the read operation and the restore operation. Hence, it is very difficult to reduce the write cycle. It is to be noted that FIG. 4 shows that the read cycle has the same cycle as the write cycle. However, the time necessary to read data is half the time necessary to write data.